A DRAM memory is a random address volatile memory type the memory cells of which lose their contents within a certain period of time even when applying a supply voltage and therefore necessitates refreshing or renewal of the memory contents at fixed intervals. A basic principle of dynamic memory is realizing individual memory cells by transistors and capacitor elements using highly integrated circuits based on silicon. Every memory cell represents an individual bit in the form of a logic zero or one. Due to a small number of elements per memory cell, the DRAM technology is most suitable to achieve high memory capacity on little space. A disadvantage of the dynamic RAM is that a piece of information stored in the cells only persists for a very short time and has to be refreshed continuously by relatively complicated mechanisms.
Memory cells of dynamic memory elements are realized as memory capacitances by separating two well-conducting layers of the largest area possible by a high-resistance dielectric as thin as possible. In a technological realization of these minimal structures, a plurality of high-resistance leakage current paths to the surroundings of a cell or via the dielectric of the memory cell itself cannot be avoided. The high-resistance leakage current paths which are strongly dependent on temperature may result in a discharge of the charge stored in a memory capacitance of a memory cell and thus result in a data loss of the memory cell. In order to be able to reliably read out the memory cell with correct data contents, a residual charge in the memory cell must not fall below a predetermined level. The data contents of the memory cells and/or a sufficient cell residual charge can be guaranteed when refreshing, that is recharging, the memory cell within a defined time. A time interval between two successive refreshes of a memory cell while still being able to read out the cell information correctly, is referred to as retention time.
A memory field and/or a memory matrix of DRAMs includes rows (word lines) and columns (bit lines). When a memory is accessed, a word line is generally enabled at first. Thus, the memory cells arranged in a row are each connected to a bit line in a conducting manner. The charge of a cell is divided into cell and bit line capacitance. Corresponding to the ratio of the two capacitances (transfer ratio), this results in a deflection of a bit line voltage. A primary sense amplifier (SA) which exemplarily compares and subsequently amplifies this bit line voltage to a constant voltage on a reference bit line is arranged at the end of the bit line.
DRAM memory elements may be placed in different operating modes and can be operated correspondingly. A so-called self-refresh mode of DRAM memory elements is, for example, employed to save current, in particular in laptop applications. When an application is in a standby mode, DRAM memory modules can be placed in a sleep mode where the memory element itself provides for maintaining the charge of its data, instead of the application. Thus, the application does not have to communicate additional commands or addresses to the memory element. Charge retention is ensured by chip-internal refresh commands. Suitable intervals between the refresh commands guarantee a sufficient charge in the memory cells which can result in a correct evaluation of the cell contents. If the intervals between the internal refresh commands are selected to be too short, the danger of data loss will decrease, however the current consumption during the current-saving mode will increase. If, however, the time intervals between the refresh commands are selected to be too great in order to achieve a low operating current, the risk of data loss in the self-refresh mode will increase correspondingly.